1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a high-speed read mode.
2. Description of the Prior Art
As the processing speed of microprocessors have been remarkably improved in recent years, a semiconductor memory device is increasingly required to operate at a high speed. Accordingly, some improved semiconductor memory devices have been developed (for example, "A 20ns 1Mb CMOS Burst Mode EPROM" by B. ASHMORE et al., 1989 IEEE International Solid-State Circuit Conference). These devices perform the normal random access more rapidly, and have a high-speed read mode. In the high-speed read mode, the read operation can be performed more rapidly, though the access methods are limited somewhat.
FIG. 5 shows a prior art mask ROM (Read Only Memory) which has such a high-speed read mode. In the mask ROM, one column select line C.sub.i is designated by decoding high order bits of an input address. Then, a plurality of transistors Q.sub.i0 -Q.sub.in in a data line selection circuit 11 are turned on, so as to select a plurality of data lines D.sub.i0 -D.sub.in corresponding thereto. Any one row select line W.sub.j is designated by decoding low order bits except for the least significant bits of the input address. One column select line C.sub.i and one row select line W.sub.j are designated, so that a plurality of memory cells 12 are simultaneously selected.
The memory cells 12 comprise transistors Q.sub.ij0 -Q.sub.ijn, respectively. Each of these transistors Q.sub.ij0 -Q.sub.ijn is a MOSFET, and is formed in a semiconductor fabricating process in such a manner that the threshold voltage thereof is high when storing logical "1", and the threshold voltage becomes similar to that of the normal enhancement type when storing logical "0". Therefore, when one row select line W.sub.j is designated to become HIGH, the transistors Q.sub.ij0 -Q.sub.ijn of memory cells 12 corresponding to the column select line W.sub.j are normally off ("1") or normally on ("0"), in accordance with the logic state.
When the plurality of transistors Q.sub.i0 -Q.sub.in in the data line selection circuit 11 are turned on by the designation of the column select line C.sub.i, the transistors Q.sub.ij0 -Q.sub.ijn of memory cells 12 selected by the row select line W.sub.j are connected to sense amplifiers 13, respectively. As a result, the potentials of the data lines D.sub.i0 -D.sub. in selected by the column select line C.sub.i gradually change to HIGH ("1") or LOW ("0"), respectively, in accordance with the logic states of the connected transistors Q.sub.ij0 -Q.sub.ijn . These weak potentials are amplified by the respective sense amplifiers 13, in order to be valid.
In the normal random access, one of bank select lines P.sub.0 -P.sub.n is designated to be HIGH in accordance with the least significant bits of the input address. Thus, only one of transistors Q.sub.p0 -Q.sub.pn in a switching circuit 14 is turned on through which the output of the sense amplifier 13 connected to the corresponding one of data lines D.sub.i0 -D.sub.in is sent out to an output buffer 15. Therefore, in the normal random access, the logic state stored in one memory cell 12 designated by the input address can be read out via the output buffer 15.
When the logic state of memory cell 12 is read out through the corresponding one of the data lines D.sub.i0 -D.sub.in in this way, also the potentials at the remaining data lines D.sub.i0 -D.sub.in which are not selected by the switching circuit 14 have already become valid by the respective sense amplifiers 13. In this condition, when another one of the bank select lines P.sub.0 -P.sub.n is switched to be HIGH, the logic state of the corresponding memory cell 12 can be immediately read out without waiting for the potentials of the data lines D.sub.i0 -D.sub.in to be valid. Therefore, in the high-speed read mode, for example, the; least significant bits of the input address are automatically generated by an address counter, etc., so that the bank select lines P.sub.0 -P.sub.n are sequentially switched to be HIGH, whereby the transistors Q.sub.p0 -Q.sub.pn in the switching circuit 14 are sequentially turned on. Thus, the logic states of a plurality of memory cells 12 are sequentially read out through the plurality of data lines D.sub.i0 - D.sub.in simultaneously selected by one column select line C.sub.i.
As shown in FIG. 6, the input address becomes valid at time t.sub.10. In response to this, one column select line C.sub.i and one column select line W.sub.j are designated to be HIGH. Then, the data lines D.sub.i0 -D.sub.in are connected to the respective sense amplifiers 13, and the potentials of the data lines D.sub.i0 -D.sub.in change to be valid at time t.sub.11. Since the bank select line P.sub.0 has been designated to be HIGH at this time, the output of the sense amplifier 13 connected to the data line D.sub.i0 is sent out to the output buffer 15. Next, the bank select line P.sub.1 is switched to be HIGH at time t.sub.12, and the output of the sense amplifier 13 connected to the data line D.sub.i1 is sent out to the output buffer 15. Thereafter, the bank select lines P.sub.2 -P.sub.n are sequentially switched to be HIGH, so that the outputs of the sense amplifiers 13 connected to the corresponding data lines D.sub.i2 -D.sub.in are sent out to the output buffer 15.
As a result, the reading from the first memory cell 12 comprising the transistor Q.sub.ij0 requires the time period of t.sub.11 -t.sub.10 which continues until the potential of the data line D.sub.i0 becomes valid, as in the normal random access. On the contrary, since the potentials of the data lines D.sub.i1-D.sub.in simultaneously selected are already valid, the logic states of the corresponding memory cells 12 respectively comprising transistors Q.sub.ij1 -Q.sub.ijn can be immediately read out by switching the bank select lines P.sub.1 -P.sub.n in the succeeding readings.
However, in the above-mentioned prior art semiconductor memory device, it is required to provide the sense amplifiers 13 respectively on all data lines D.sub.i0 -D.sub.in which are simultaneously selected by one column select line C.sub.i, in order to set a high-speed read mode. Therefore, as the number of bits which can be simultaneously read out for a high speed reading increases, the number of sense amplifiers 13 must be increased. This causes the occupied area on a chip and the power consumption to increase.
Therefore, the prior art semiconductor memory device with a high-speed read mode has a problem in that if the number of bits which are simultaneously read out increases, the chip area and the power consumption increase.